Приложение б. Подробный отчёт синтеза
Приложение в. Аппаратная имплементация инфраструктуры тестированиия
ЛистингB.1. Протокол синтеза модуля диагностирования
=====================================================================
* Synthesis Options Summary *
=========================================================================
Input File Name : "diagnosis.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "diagnosis"
Output Format : NGC
Target Device : xc3s1200e-4-fg400
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s1200e.nph' in environment D:\Xilinx92i.
=========================================================================
Advanced HDL Synthesis Report
# Counters : 1
4-bit up counter : 1
# Registers : 321
Flip-Flops : 321
# Multiplexers : 1
16-bit 16-to-1 multiplexer : 1
=========================================================================
* Final Report *
=========================================================================
RTL Top Level Output File Name : diagnosis.ngr
Top Level Output File Name : diagnosis
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 292
Cell Usage :
# BELS : 277
# INV : 1
# LUT2 : 17
# LUT3 : 145
# LUT4 : 2
# MUXF5 : 64
# MUXF6 : 32
# MUXF7 : 16
# FlipFlops/Latches : 336
# FDC : 64
# FDCE : 272
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 291
# IBUF : 274
# OBUF : 17
MAP REPORT
Command Line : D:\Xilinx92i\bin\nt\map.exe -ise
D:/My_Designs/Xilinx/Vova/Vova.ise -intstyle ise -p xc3s1200e-fg400-4 -cm
-pr b -k 4 -c 100 -o diagnosis_map.ncd diagnosis.ngd diagnosis.pcf
Target Device : xc3s1200e
Target Package : fg400
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.36 $
Mapped Date : Sun May 29 19:00:07 2011
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 47 out of 17,344 1%
Number of 4 input LUTs: 164 out of 17,344 1%
Logic Distribution:
Number of occupied Slices: 110 out of 8,672 1%
Number of Slices containing only related logic: 110 out of 110 100%
Number of Slices containing unrelated logic: 0 out of 110 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 164 out of 17,344 1%
Number of bonded IOBs: 292 out of 304 96%
IOB Flip Flops: 289
Number of GCLKs: 1 out of 24 4%
Total equivalent gate count for design: 4,011
Additional JTAG gate count for IOBs: 14,016
Peak Memory Usage: 160 MB
Total REAL time to MAP completion: 5 secs
Total CPU time to MAP completion: 3 secs
Листинг B.2. Протокол синтеза модуля оптимизации
OPTIMIZATION
=========================================================================
* Synthesis Options Summary *
=========================================================================
Input File Name : "optimization.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
Output File Name : "optimization"
Output Format : NGC
Target Device : xc3s1200e-4-fg400
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <optimization>.
Related source file is "D:/My_Designs/Xilinx/optimization/optimization.vhd".
Found 1-bit register for signal <done>.
Found 256-bit register for signal <B>.
Found 16-bit 16-to-1 multiplexer for signal <B_i>.
Found 4-bit up counter for signal <cnt>.
Found 16-bit register for signal <ma>.
Found 16-bit register for signal <mb>.
Summary:
inferred 1 Counter(s).
inferred 289 D-type flip-flop(s).
inferred 16 Multiplexer(s).
Unit <optimization> synthesized.
=========================================================================
HDL Synthesis Report
# Counters : 1
4-bit up counter : 1
# Registers : 4
1-bit register : 1
16-bit register : 2
256-bit register : 1
# Multiplexers : 1
16-bit 16-to-1 multiplexer : 1
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Loading device for application Rf_Device from file '3s1200e.nph' in environment D:\Xilinx92i.
=========================================================================
Advanced HDL Synthesis Report
# Counters : 1
4-bit up counter : 1
# Registers : 289
Flip-Flops : 289
# Multiplexers : 1
16-bit 16-to-1 multiplexer : 1
MAP REPORT
Command Line : D:\Xilinx92i\bin\nt\map.exe -ise
D:/My_Designs/Xilinx/optimization/optimization.ise -intstyle ise -p
xc3s1200e-fg400-4 -cm area -pr b -k 4 -c 100 -o optimization_map.ncd
optimization.ngd optimization.pcf
Target Device : xc3s1200e
Target Package : fg400
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.36 $
Mapped Date : Sun May 29 19:39:50 2011
Design Summary
--------------
Number of errors: 0
Number of warnings: 2
Logic Utilization:
Number of Slice Flip Flops: 31 out of 17,344 1%
Number of 4 input LUTs: 164 out of 17,344 1%
Logic Distribution:
Number of occupied Slices: 94 out of 8,672 1%
Number of Slices containing only related logic: 94 out of 94 100%
Number of Slices containing unrelated logic: 0 out of 94 0%
*See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs: 164 out of 17,344 1%
Number of bonded IOBs: 292 out of 304 96%
IOB Flip Flops: 273
Number of GCLKs: 1 out of 24 4%
Total equivalent gate count for design: 3,707
Additional JTAG gate count for IOBs: 14,016
Peak Memory Usage: 160 MB
Total REAL time to MAP completion: 4 secs
Total CPU time to MAP completion: 3 secs
Листинг B.3. HDL-код синтеза модуля выполнения операций
timescale 1 ns / 1 ps
`define n 4
`define m 4
module LU
( input direction,
input [`m*`n-1:0] R0_in, input [`m-1:0] R1_in,
input [`n-1:0] R2_in, input clk, rst,
input Load_R0, Load_R1, Load_R2, Load_R, Load_R3,
input rst_R, rst_R3, R2_sel,
output [`n-1:0] R2, output R3);
reg [`m*`n-1:0] R0_reg, R0_w; reg [`m-1:0] R1_reg;
reg [`n-1:0] R2_reg, R_reg; reg R3_reg, rstR_reg;
wire [`n-1:0] R_w, R2_w; wire R3_w;
integer temp1, temp2, ii, j;
generate
genvar i;
for (i = 0; i <`n; i=i + 1) begin: xi
assign R_w[i]=|(R0_reg[(i+1)*`m-1:`m*i]& R1_reg);
end
endgenerate
assign R2_w = (~R2_sel)? R2_in: (R_reg&R2_reg);
assign R3_w = (R2_reg == R2_w)? 0: 1;
///////// OUTPUTS ///////////
assign R2 = R2_reg; assign R3 = R3_reg;
always @(*) begin
temp1=`n*`n;
if (direction==0) R0_w = R0_in;
else //decoder
for(ii=`n; ii>0; ii=ii-1) for(j=`n; j>0; j=j-1) begin
temp1=temp1-1; temp2= (j-1)*`n+ii-1;
R0_w[temp1] = R0_in[temp2];
end end
// Registers
always @(posedge rst, posedge clk)
if (rst) R0_reg = 0;
else if (Load_R0) R0_reg = R0_w;
always @(posedge rst, posedge clk)
if (rst) R1_reg = 0;
else if (Load_R1) R1_reg = R1_in;
always @(posedge rst, posedge clk)
if (rst) R2_reg = 0;
else if (Load_R2) R2_reg = R2_w;
always @(posedge clk)
if (rst_R) rstR_reg = 1;
else rstR_reg = 0;
always @(posedge rst, posedge clk)
if (rst) R_reg = 0;
else if (Load_R && rst_R) R_reg = R_w;
else if (Load_R) R_reg = R_w | R_reg;
always @(posedge rst, posedge clk)
if (rst) R3_reg = 0;
else if (rst_R3) R3_reg = 0;
else if (Load_R3) R3_reg = R3_w | R3_reg;
endmodule
Selected Device : 3s500ecp132-5
Number of Slices: 20 out of 4656 0%
Number of Slice Flip Flops: 29 out of 9312 0%
Number of 4 input LUTs: 35 out of 9312 0%
Number of IOs: 40
Number of bonded IOBs: 40 out of 92 43%
Number of GCLKs: 1 out of 24 4%